pb-free available sip42101 vishay siliconix new product document number: 73176 s-50265?rev. b, 21-feb-05 www.vishay.com 1 half-bridge n-channel mosfet driver for motor control features applications 5-v gate drive undervoltage lockout internal bootstrap diode adaptive shoot-through protection motor braking shutdown control matched rising and falling propagation delays drive mosfets in 4.5- to 50-v systems h-bridge motor controls 3-phase motor controls description the sip42101 is a high-speed half-bridge mosfet driver with adaptive shoot-through protection for motor driving applications. the high-side driver is bootstrapped to allow driving n-channel mosfets. the brake pin forces the lowside mosfet on, providing a braking function in h-bridge and 3-phase topologies. the sip42101 comes with adaptive shoot-through protection to prevent simultaneous conduction of the external mosfets. the sip42101 is available in both standard and lead (pb)-free 10-pin mlp33 packages and is specified to operate over the industrial temperature range of ? 40 c to 85 c. functional block diagram controller pwm gnd v dd motor winding gnd gnd +5 v +5 to 50 v boot out h lx out l sip42101 brake sd
sip42101 vishay siliconix new product www.vishay.com 2 document number: 73176 s-50265?rev. b, 21-feb-05 absolute maximum ratings (all voltages referenced to gnd = 0 v) v dd , pwm, sd , brake 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lx, boot 55 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . boot to lx 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ? 40 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation a,b mlp-33 960 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) a,b mlp-33 105 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. device mounted with all leads soldered or welded to pc board. a. derate 9.6 mw/ c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range (all voltages referenced to gnd = 0 v) v dd 4.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v boot 4.5 v to 50 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c boot 100 nf to 1 f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature range ? 40 to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . specifications a test conditions unless specified limits parameter symbol v dd = 5 v, v boot ? v lx = 5 v, c load = 3 nf t a = ? 40 to 85 c min a typ b max a unit power supplies supply voltage v dd 4.5 5.5 v quiescent current i ddq f pwm = 1 mhz, c load = 0 2.2 3.0 ma shutdown current i sd 1 a reference voltage break-before-make v bbm 1 v pwm input input high v ih 4.0 v dd v input low v il 0.5 v bias current i b 0.3 1 a sd , brake inputs input high v ih 2.0 v dd v input low v il 1.0 v bias current brake i b 1 a bias current sd i b sd = 5 v 3.5 7 a high-side undervoltage lockout threshold v uvhs rising or falling 2.5 3.35 3.75 v bootstrap diode forward voltage v f i f = 10 ma, t a = 25 c 0.70 0.76 0.82 v mosfet drivers high - side drive current c i pkh(source) 0.9 hi g h - sid e d r i ve c urrent c i pkh(sink) 1.1 a low - side drive current c i pkl(source) 0.8 a l ow- sid e d r i ve c urrent c i pkl(sink) 1.5 high side driver impedance r dh(source) 2.5 3.8 high-side driver impedance r dh(sink) 2.2 3.3 low side driver impedance r dl(source) 3.4 5.1 low-side driver impedance r dl(sink) 1.4 2.1
sip42101 vishay siliconix new product document number: 73176 s-50265?rev. b, 21-feb-05 www.vishay.com 3 specifications a limits test conditions unless specified v dd = 5 v, v boot ? v lx = 5 v, c load = 3 nf t a = ? 40 to 85 c parameter unit max a typ b min a test conditions unless specified v dd = 5 v, v boot ? v lx = 5 v, c load = 3 nf t a = ? 40 to 85 c symbol mosfet drivers high-side rise time t rh 10% ? 90% 32 40 high-side fall time t fh 90% ? 10% 36 45 high side propagation delay c t d(off)h see timing w aveforms 20 high-side propagation delay c t d(on)h see timing w aveforms 30 ns low-side rise time t rl 10% ? 90% 45 55 ns low-side fall time t fl 90% ? 10% 20 30 low side propagation delay c t d(off)l see timing w aveforms 30 low-side propagation delay c t d(on)l see timing w aveforms 30 lx timer lx falling timeout c t lx 420 ns v dd undervoltage lockout threshold rising v uvlor 4.35 4.5 threshold falling v uvlof 3.7 4.1 v hysteresis v h 0.4 power on reset time c 2.5 ms thermal shutdown temperature t sd temperature rising 165 c hysteresis t h temperature falling 25 c notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum ( ? 40 to 85 c). b. typical values are for design aid only, not guaranteed nor subject to production testing and are measured at v dd = 5v unless otherwise noted. c. guaranteed by design. timing waveforms t d(off)h t d(off)l pwm out h out l t d(on)l t d(on)h 10% 90% 50% 90% 10% 10% 10% 50% 90% 90% t fl t rh t rl t fh
2 3 4 10 9 8 7 out h boot pwm sd lx brake nc v dd top view 5 gnd 6 out l mlp33 sip42101 vishay siliconix new product www.vishay.com 4 document number: 73176 s-50265?rev. b, 21-feb-05 pin configuration and truth table truth table pwm sd brake out h out l l h l l h h h l h l x h h l h x l x l l ordering information standard part number lead(pb)-free part number temperature range marking sip42101dm-t1 sip42101dm-t1?e3 ? 40 to 85 c 42101 eval kit temperature range sip42101db ? 40 to 85 c pin description pin number name function 1 out h high-side mosfet gate drive 2 boot bootstrap supply for high-side driver. a capacitor connects between boot and lx. 3 pwm input signal for the mosfet drivers 4 sd shuts down the driver 5 gnd ground 6 out l synchronous or low-side mosfet gate drive 7 v dd +5-v supply 8 nc no connect 9 brake forces out l high and out h low 10 lx connection to source of high-side mosfet, drain of the low-side mosfet, and the inductor
sip42101 vishay siliconix new product document number: 73176 s-50265?rev. b, 21-feb-05 www.vishay.com 5 functional block diagram figure 1. pwm gnd v dd out h lx out l otp v dd boot v bbm ? + uvlo sd brake detailed operation pwm the pwm pin controls the switching of the external mosfets. the driver logic operates in a noninverting configuration. the pwm input stage should be driven by a signal with fast transition times, like those provided by a pwm controller or logic gate, (<200 ns). the pwm input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a switching output when the input switching threshold voltage is reached. low-side driver the supplies for the low-side driver are v dd and gnd. during shutdown, out l is held low. high-side driver the high-side driver is isolated from the substrate to create a floating high-side driver so that an n-channel mosfet can be used for the high-side switch. the supplies for the high-side driver are boot and lx. the voltage is supplied by a floating bootstrap capacitor, which is continually recharged by the switching action of the output. during shutdown out h is held low. bootstrap circuit the internal bootstrap diode and a bootstrap capacitor form a charge pump that supplies voltage to the boot pin. an integrated bootstrap diode replaces the external schottky diode needed for the bootstrap circuit; only a capacitor is necessary to complete the bootstrap circuit. the bootstrap capacitor is sized according to, c boot = (q gate / v boot ? lx ) x 10 where q gate is the gate charge needed to turn on the high-side mosfet and v boot ? lx is the amount of droop allowed in the bootstrapped supply voltage when the high-side mosfet is driven high. the bootstrap capacitor value is typically 0.1 f to 1 f. the bootstrap capacitor voltage rating must be greater than v dd + 5 v to withstand transient spikes and ringing. shoot-through protection the external mosfets are prevented from conducting at the same time during transitions. break-before-make circuits monitor the voltages on the lx pin and the out l pin and control the switching as follows: when the signal on pwm goes low, out h will go low after an internal propagation delay . after the voltage on lx falls below 1 v by the inductor action, the low-side driver is enabled and out l goes high after some delay. when the signal on pwm goes high, out l will go low after an internal propagation delay. after the voltage on out l drops below 1 v the high-side driver is enabled and out h will go high after an internal propa gation delay. if lx does not drop below 1 v within 400 ns after out h goes low, out l is forced high until the next pwm transition.
sip42101 vishay siliconix new product www.vishay.com 6 document number: 73176 s-50265?rev. b, 21-feb-05 matched propagation delays rising and falling propagation delays are matched from pwm to lx to within 8 ns. brake input when brake is high, out h is forced low and out l is forced high to create active braking of the motor. when this input is low, operation is normal. shutdown the driver enters shutdown mode when sd is low. shutdown current is less than 1 a. v dd bypass capacitor mosfet drivers draw large peak currents from the supplies when they switch. a local bypass capacitor is required to supply this current and reduce power supply noise. connect a 1- f ceramic capacitor as close as practical between the v dd and gnd pins. undervoltage lockout undervoltage lockout prevents control of the circuit until the supply voltages reach valid operating levels. the uvlo circuit forces out l and out h to low when v dd is below its specified voltage. a separate uvlo forces out h low when the voltage between boot and lx is below the specified voltage. thermal protection if the die temperature rises above 165 c, the thermal protection disables the drivers. the drivers are re-enabled after the die temperature has decreased below 140 c. typical characteristics 0 10 20 30 40 50 012345 i dd vs. c load vs. frequency c load (nf) 1 mhz i dd (ma) 500 khz 200 khz
sip42101 vishay siliconix new product document number: 73176 s-50265?rev. b, 21-feb-05 www.vishay.com 7 typical waveforms 50 ns/div figure 2. pwm signal vs. lx (rising) figure 3. pwm signal vs. lx (falling) figure 4. pwm signal vs. hs gate and ls gate (rising) figure 6. brake enable 10 s/div pwm in 2 v/div v lx 2 v/div 50 ns/div pwm in 2 v/div v lx 2 v/div 50 ns/div pwm in 5 v/div hs gate 5 v/div ls gate 5 v/div figure 5. pwm signal vs. hs gate and ls gate (falling) 50 ns/div pwm in 5 v/div hs gate 5 v/div ls gate 5 v/div v brake 5 v/div hs gate 5 v/div ls gate 2 v/div vishay siliconix maintains worldw ide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?73176 .
legal disclaimer notice vishay document number: 91000 www.vishay.com revision: 08-apr-05 1 notice specifications of the products displayed herein are subjec t to change without notice. vishay intertechnology, inc., or anyone on its behalf, assume s no responsibility or liability fo r any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in vishay's terms and conditions of sale for such products, vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and /or use of vishay products including liab ility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrigh t, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify vishay for any damages resulting from such improper use or sale.
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